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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車(chē)應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

I2C voltage translation and repeaters

Today's electronic systems are significantly more complex. This is clearly visible with the increased complexity found in I2C-bus communications. For I2C master/slave interfaces there is a trend towards higher bus speed (standard, Fast-mode, FM+), with multi-voltage bus branches common and a need for support of clock-stretching. Regardless of the complexity, Nexperia can offer a solution to meet your needs.

Block diagram

Highlighted components are Nexperia focus products

Design considerations

  • Potential for high capacitive bus load, handling FM+ speed (1 MHz)
  • I2C master and slaves operating from 0.8 V to 5 V
  • Need to split or separate I2C branches
  • Support for clock-stretching

Logic Application Handbook

Download Nexperia’s Logic Design Engineer’s Guide and get a better understanding of Logic products, their features and properties, timing and interfacing aspects as well as get an overview of application insights.

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2022版選型指南

2022版Nexperia選型指南在單個(gè)文檔中展示了我們所有的分立器件、邏輯器件和MOSFET器件，讓您可以全面了解我們的產(chǎn)品組合，幫助您更加容易找到適合您設(shè)計(jì)的產(chǎn)品。

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