可訂購部件
型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
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74AHC595BQ | 74AHC595BQ,115 | 935281621115 | SOT763-1 | 訂單產(chǎn)品 |
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Click here for more information8-bit serial-in/serial-out or parallel-out shift register with output latches
The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The 74AHCT595 features TTL compatible inputs. Both 74AHC595 and 74AHCT595 inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
Wide supply voltage range from 2.0 V to 5.5 V
Balanced propagation delays
All inputs have Schmitt-trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Input levels:
The 74AHC595 operates with CMOS input levels
The 74AHCT595 operates with TTL input levels
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Serial-to-parallel data conversion
Remote control holding register
型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
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74AHC595BQ | 2.0?-?5.5 | CMOS | ± 8 | 4.0 | 170 | 8 | low | -40~125 | DHVQFN16 |
Model Name | 描述 |
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型號 | 可訂購的器件編號,(訂購碼(12NC)) | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
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74AHC595BQ | 74AHC595BQ,115 (935281621115) |
Active | AHC595 |
DHVQFN16 (SOT763-1) |
SOT763-1 | SOT763-1_115 |
型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
---|---|---|---|---|
74AHC595BQ | 74AHC595BQ,115 | 74AHC595BQ |
文件名稱 | 標(biāo)題 | 類型 | 日期 |
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74AHC_AHCT595 | 8-bit serial-in/serial-out or parallel-out shift register with output latches | Data sheet | 2024-03-07 |
AN11106 | Pin FMEA for AHC/AHCT family | Application note | 2019-01-09 |
SOT763-1 | 3D model for products with SOT763-1 package | Design support | 2019-10-03 |
ahc595 | ahc595 IBIS model | IBIS model | 2013-04-08 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
DHVQFN16_SOT763-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
SOT763-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 1 mm body | Package information | 2023-05-11 |
SOT763-1_115 | DHVQFN16; Reel pack, SMD, 7" Q1/T1 product orientation | Packing information | 2020-04-21 |
74AHC595BQ_Nexperia_Product_Reliability | 74AHC595BQ Nexperia Product Reliability | Quality document | 2024-06-16 |
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Model Name | 描述 |
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型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
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74AHC595BQ | 74AHC595BQ,115 | 935281621115 | Active | SOT763-1_115 | 3,000 | 訂單產(chǎn)品 |
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The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.