74ALVCH16374DGG

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip?-?flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF-state. Operation of the nOE input does not affect the state of the flip?-?flops.

This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
MULTIBYTE? flow-through standard pin-out architecture
Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Latch-up performance exceeds 100 mA per JESD 78 Class II.A
Output drive capability 50 Ω transmission lines at 85 °C
I_OFF circuitry provides partial Power-down mode operation
Current drive ±24 mA at V_CC = 3.0 V
Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C

參數(shù)類型

型號	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	Package name
74ALVCH16374DGG	1.2?-?3.6	TTL	± 24	2.3	350	low	-40~85	TSSOP48

PCB Symbol, Footprint and 3D Model

Model Name	描述

封裝

型號	可訂購的器件編號，（訂購碼(12NC)）	狀態(tài)	標(biāo)示	封裝	外形圖	回流焊/波峰焊	包裝
74ALVCH16374DGG	74ALVCH16374DGG:11 (935205130118)	Active	ALVCH16374	TSSOP48 (SOT362-1)	SOT362-1	SSOP-TSSOP-VSO-WAVE	SOT362-1_118

環(huán)境信息

型號	可訂購的器件編號	化學(xué)成分	RoHS	RHF指示符
74ALVCH16374DGG	74ALVCH16374DGG:11	74ALVCH16374DGG

品質(zhì)及可靠性免責(zé)聲明

Series

文檔 (9)

文件名稱	標(biāo)題	類型	日期
74ALVCH16374	2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state	Data sheet	2024-06-19
SOT362-1	3D model for products with SOT362-1 package	Design support	2020-01-22
alvch16374	alvch16374 IBIS model	IBIS model	2013-04-08
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
TSSOP48_SOT362-1_mk	plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body	Marcom graphics	2017-01-28
SOT362-1	plastic thin shrink small outline package; 48 leads; body width 6.1 mm	Package information	2024-01-05
SOT362-1_118	TSSOP48; Reel pack for SMD, 13''; Q1/T1 product orientation	Packing information	2020-04-21
74ALVCH16374DGG_Nexperia_Product_Reliability	74ALVCH16374DGG Nexperia Product Reliability	Quality document	2024-06-16
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08

支持

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模型

文件名稱	標(biāo)題	類型	日期
alvch16374	alvch16374 IBIS model	IBIS model	2013-04-08
SOT362-1	3D model for products with SOT362-1 package	Design support	2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name	描述

訂購、定價與供貨

型號	Orderable part number	Ordering code (12NC)	狀態(tài)	包裝	Packing Quantity	在線購買
74ALVCH16374DGG	74ALVCH16374DGG:11	935205130118	Active	SOT362-1_118	2,000	訂單產(chǎn)品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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