可訂購部件
型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
---|---|---|---|---|
74ALVCH16543DGG | 74ALVCH16543DGG,11 | 935262544118 | SOT364-1 | 訂單產(chǎn)品 |
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Click here for more information16-bit D-type registered transceiver; 3-state
TThe 74ALVCH16543 is a 16-bit registered transceiver with bus hold inputs and 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver.
Data flow in each direction is controlled by intput enable (nEAB and nEBA), latch enable (nLEAB and nLEBA), and output enable (nOEAB and nOEBA) inputs. For A to B data flow, the device operates in the transparen mode when (nEAB) and (nLEAB) are LOW. A subsequent LOW-to-HIGH transition of the nLEAB input latches the data and the outputs no longer change with the inputs. A HIGH on either nEAB or nOEAB causes the outputs to assume a high-impedance OFF-state.
Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Wide supply voltage range from 1.65 V to 3.6 V
CMOS low power dissipation
Direct interface with TTL levels
MULTIBYTE? flow-through standard pin-out architecture
Back-to-back registers for storage
Output drive capability 50 Ω transmission lines at 85 °C
All data inputs have bushold
Low inductance multiple VCC and GND pins for minimize noise and ground bounce
Current drive ±24 mA at VCC = 3.0 V.
3-state non-inverting outputs for bus oriented applications
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
ESD protection:
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
型號 | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|---|---|
74ALVCH16543DGG | n.a. | n.a. | TTL | ± 24 | 3.8 | 16 | 150 | low | -40~85 | TSSOP56 |
型號 | 可訂購的器件編號,(訂購碼(12NC)) | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
---|---|---|---|---|---|---|---|
74ALVCH16543DGG | 74ALVCH16543DGG,11 (935262544118) |
Active | ALVCH16543 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT364-1_118 |
型號 | 可訂購的器件編號 | 化學(xué)成分 | RoHS | RHF指示符 |
---|---|---|---|---|
74ALVCH16543DGG | 74ALVCH16543DGG,11 | 74ALVCH16543DGG |
文件名稱 | 標(biāo)題 | 類型 | 日期 |
---|---|---|---|
74ALVCH16543 | 16-bit D-type registered transceiver; 3-state | Data sheet | 2024-07-03 |
SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
alvch16543 | alvch16543 IBIS model | IBIS model | 2013-04-08 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
SOT364-1_118 | TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2020-04-21 |
74ALVCH16543DGG_Nexperia_Product_Reliability | 74ALVCH16543DGG Nexperia Product Reliability | Quality document | 2024-06-16 |
SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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文件名稱 | 標(biāo)題 | 類型 | 日期 |
---|---|---|---|
alvch16543 | alvch16543 IBIS model | IBIS model | 2013-04-08 |
SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
---|---|---|---|---|---|---|
74ALVCH16543DGG | 74ALVCH16543DGG,11 | 935262544118 | Active | SOT364-1_118 | 2,000 | 訂單產(chǎn)品 |
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The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.