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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車(chē)應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74AUP1G885GF

Low-power dual function gate

The 74AUP1G885 is a dual function gate. The output state of the outputs (1Y, 2Y) is determined by the inputs (A, B and C). The output 1Y provides the Boolean function: 1Y = A × C. The output 2Y provides the Boolean function: 2Y = A × B + A × C.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 100 mA per JESD78 Class II

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類(lèi)型

型號(hào) Package name
74AUP1G885GF XSON8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào),(訂購(gòu)碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP1G885GF 74AUP1G885GF,115
(935291472115)
Withdrawn / End-of-life 58 SOT1089
XSON8
(SOT1089)
SOT1089 REFLOW_BG-BD-1
SOT1089_115

環(huán)境信息

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74AUP1G885GF 74AUP1G885GF,115 74AUP1G885GF rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (12)

文件名稱(chēng) 標(biāo)題 類(lèi)型 日期
74AUP1G885 Low-power dual function gate Data sheet 2024-08-12
AN11052 Pin FMEA for AUP family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT1089 3D model for products with SOT1089 package Design support 2019-10-07
aup1g885 aup1g885 IBIS model IBIS model 2013-04-07
Nexperia_document_Logic_CombinationLogic_infocard_201710 Combination logic solutions card Leaflet 2019-08-09
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
XSON8_SOT1089_mk plastic, extremely thin small outline package; no leads; 8 terminals; 0.55 mm pitch; 1.35 mm x 1 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT1089 plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm body Package information 2022-06-03
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT1089 MAR_SOT1089 Topmark Top marking 2013-06-03

支持

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模型

文件名稱(chēng) 標(biāo)題 類(lèi)型 日期
aup1g885 aup1g885 IBIS model IBIS model 2013-04-07
SOT1089 3D model for products with SOT1089 package Design support 2019-10-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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