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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVC1G175GF

Single D-type flip-flop with reset; positive-edge trigger

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.

The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

此產品已停產

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V

  • High noise immunity

  • Overvoltage tolerant inputs to 5.5 V

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C.

參數類型

型號 Package name
74LVC1G175GF XSON6

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC1G175GF 74LVC1G175GF,132
(935282414132)		 Obsolete YT SOT891
XSON6
(SOT891) 		SOT891 REFLOW_BG-BD-1
SOT891_132

環(huán)境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVC1G175GF 74LVC1G175GF,132 74LVC1G175GF rohs rhf rhf
品質及可靠性免責聲明

文檔 (11)

文件名稱 標題 類型 日期
74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Data sheet 2023-08-15
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11009 Pin FMEA for LVC family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT891 3D model for products with SOT891 package Design support 2019-10-03
lvc1g175 74LVC1G175 IBIS model IBIS model 2014-10-20
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DFN1010-6_SOT891_mk plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT891 plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body Package information 2020-04-21
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT891 MAR_SOT891 Topmark Top marking 2013-06-03

支持

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模型

文件名稱 標題 類型 日期
lvc1g175 74LVC1G175 IBIS model IBIS model 2014-10-20
SOT891 3D model for products with SOT891 package Design support 2019-10-03

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.