可訂購部件
型號(hào) | 可訂購的器件編號(hào) | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
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74LVC374ABQ | 74LVC374ABQ,115 | 935273479115 | SOT764-1 | 訂單產(chǎn)品 |
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Click here for more informationOctal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
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74LVC374ABQ | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 2.7 | 100 | low | -40~125 | DHVQFN20 |
Model Name | 描述 |
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型號(hào) | 可訂購的器件編號(hào),(訂購碼(12NC)) | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
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74LVC374ABQ | 74LVC374ABQ,115 (935273479115) |
Active | LVC374A |
DHVQFN20 (SOT764-1) |
SOT764-1 | SOT764-1_115 |
型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
---|---|---|---|---|
74LVC374ABQ | 74LVC374ABQ,115 | 74LVC374ABQ |
文件名稱 | 標(biāo)題 | 類型 | 日期 |
---|---|---|---|
74LVC374A | Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive?-?edge trigger; 3-state | Data sheet | 2023-09-01 |
AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
SOT764-1 | 3D model for products with SOT764-1 package | Design support | 2019-10-03 |
lvc374a | lvc374a IBIS model | IBIS model | 2013-04-09 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
DHVQFN20_SOT764-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 2.5 mm x 4.5 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
SOT764-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm body | Package information | 2022-06-21 |
SOT764-1_115 | DHVQFN20; Reel pack for SMD, 7''; Q1/T1 product orientation | Packing information | 2020-04-21 |
74LVC374ABQ_Nexperia_Product_Reliability | 74LVC374ABQ Nexperia Product Reliability | Quality document | 2024-06-16 |
lvc | lvc Spice model | SPICE model | 2013-05-07 |
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Model Name | 描述 |
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型號(hào) | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
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74LVC374ABQ | 74LVC374ABQ,115 | 935273479115 | Active | SOT764-1_115 | 3,000 | 訂單產(chǎn)品 |
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The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.