可訂購部件
| 型號(hào) | 可訂購的器件編號(hào) | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVC3G17DP | 74LVC3G17DP,125 | 935275564125 | SOT505-2 | 訂單產(chǎn)品 |
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Click here for more information74LVC3G17DP
Triple non-inverting Schmitt trigger with 5 V tolerant input
The 74LVC3G17 is a triple buffer with Schmitt-trigger inputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Applications
Wave and pulse shapers for highly noisy environments
參數(shù)類型
| 型號(hào) | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVC3G17DP | 1.65?-?5.5 | CMOS/LVTTL | ± 32 | 175 | 3 | low | -40~125 | TSSOP8 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封裝
| 型號(hào) | 可訂購的器件編號(hào)，（訂購碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC3G17DP | 74LVC3G17DP,125 (935275564125) |
Active | V17 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
環(huán)境信息
| 型號(hào) | 可訂購的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC3G17DP | 74LVC3G17DP,125 | 74LVC3G17DP |
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Series
文檔 (11)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC3G17 | Triple non-inverting Schmitt trigger with 5 V tolerant input | Data sheet | 2023-08-24 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| lvc3g17 | 74LVC3G17 IBIS model | IBIS model | 2015-01-15 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| SOT505-2_125 | TSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation | Packing information | 2020-04-21 |
| 74LVC3G17DP_Nexperia_Product_Reliability | 74LVC3G17DP Nexperia Product Reliability | Quality document | 2024-06-16 |
| lvc | lvc Spice model | SPICE model | 2013-05-07 |
支持
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PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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訂購、定價(jià)與供貨
| 型號(hào) | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC3G17DP | 74LVC3G17DP,125 | 935275564125 | Active | SOT505-2_125 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC3G17DP
Triple non-inverting Schmitt trigger with 5 V tolerant input
從安世半導(dǎo)體購買
| SKU | 庫存* | MOQ | 單位價(jià)格 | 數(shù)量 |
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