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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74LVCH162374ADL

16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state

The 74LVCH162374A is a 16?-?bit edge triggered flip?-?flop featuring separate D?-?type inputs for each flip?-?flop and 3?-?state outputs for bus?-?oriented applications. The device consists of two sections of 8 edge?-?triggered flip?-?flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The flip?-?flops store the state of their individual D?-?inputs that meet the set?-?up and hold time requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the flip?-?flops are available at the outputs. When OE is HIGH, the outputs go to the high?-?impedance OFF?-?state. Operation of the OE input does not affect the state of the flip?-?flops.

Bus hold on data inputs eliminates the need for external pull?-?up resistors to hold unused inputs.

To reduce line noise, 30 Ω series termination resistors are included in both high and low output stages.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power consumption

  • Multibyte flow-through standard pinout architecture

  • Multiple low inductance supply pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • All data inputs have bus hold

  • High-impedance outputs when VCC = 0 V

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購的器件編號(hào),(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74LVCH162374ADL 74LVCH162374ADL,11
(935238760112)
Obsolete no package information
74LVCH162374ADL:11
(935238760118)
Obsolete

環(huán)境信息

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74LVCH162374ADL 74LVCH162374ADL,11 74LVCH162374ADL rohs rhf rhf
74LVCH162374ADL 74LVCH162374ADL:11 74LVCH162374ADL rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (4)

文件名稱 標(biāo)題 類型 日期
74LVCH162374A 16-bit edge-triggered D-type flip-flop with 30?Ohm series termination resistors; 5 V input/output tolerant; 3?-?state Data sheet 2024-01-31
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
lvch162374a lvch162374a IBIS model IBIS model 2013-04-09

支持

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模型

文件名稱 標(biāo)題 類型 日期
lvch162374a lvch162374a IBIS model IBIS model 2013-04-09

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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