可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVT16373ADGG | 74LVT16373ADGG,118 | 935203090118 | SOT362-1 | 訂單產(chǎn)品 |
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Click here for more information74LVT16373ADGG
3.3 V 16-bit transparent D-type latch; 3-state
The 74LVT16373A is a 16?-?bit D?-?type transparent latch with 3?-?state outputs. The device can be used as two 8?-?bit transparent latches or a single 16?-?bit transparent latch. The device features two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8?-?bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D?-?input changes. When nLE is LOW the latches store the information that was present at the inputs a set?-?up time preceding the HIGH?-?to?-?LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high?-?impedance OFF?-?state. Operation of the nOE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull?-?up resistors to define unused inputs
Features and benefits
16-bit transparent latch
3-state buffers
Wide supply voltage range from 2.7 V to 3.6 V
BiCMOS high speed and output drive
Output capability: +64 mA/–32 mA
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
Live insertion/extraction permitted
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to 85 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|
| 74LVT16373ADGG | 2.7?-?3.6 | TTL | -32/+64 | 1.9 | medium | -40~85 | TSSOP48 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVT16373ADGG | 74LVT16373ADGG,118 (935203090118) |
Active | LVT16373A |
TSSOP48 (SOT362-1) |
SOT362-1 |
SSOP-TSSOP-VSO-WAVE
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SOT362-1_118 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVT16373ADGG | 74LVT16373ADGG,118 | 74LVT16373ADGG |
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Series
文檔 (10)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVT16373A | 3.3 V 16-bit transparent D-type latch; 3-state | Data sheet | 2024-07-08 |
| SOT362-1 | 3D model for products with SOT362-1 package | Design support | 2020-01-22 |
| lvt16373a | lvt16373a IBIS model | IBIS model | 2013-04-09 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP48_SOT362-1_mk | plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body | Marcom graphics | 2017-01-28 |
| SOT362-1 | plastic thin shrink small outline package; 48 leads; body width 6.1 mm | Package information | 2024-01-05 |
| SOT362-1_118 | TSSOP48; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74LVT16373ADGG_Nexperia_Product_Reliability | 74LVT16373ADGG Nexperia Product Reliability | Quality document | 2024-06-16 |
| lvt16 | lvt16 Spice model | SPICE model | 2013-05-07 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVT16373ADGG | 74LVT16373ADGG,118 | 935203090118 | Active | SOT362-1_118 | 2,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVT16373ADGG
3.3 V 16-bit transparent D-type latch; 3-state
從安世半導體購買
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