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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車(chē)應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74LVT16543ADL

3.3 V 16-bit registered transceiver; 3-state

The 74LVT16543A is a 16?-?bit registered transceiver with 3?-?state outputs. The device can be used as two 8?-?bit transceivers or one 16?-?bit transceiver.

Data flow in each direction is controlled by intput enable (nEAB and nEBA), latch enable (nLEAB and nLEBA), and output enable (nOEAB and nOEBA) inputs. For A to B data flow, the device operates in the transparent mode when (nEAB) and (nLEAB) are LOW. A subsequent LOW?-?to?-?HIGH transition of the nLEAB input latches the data and the outputs no longer change with the inputs. A HIGH on either nEAB or nOEAB causes the outputs to assume a high?-?impedance OFF?-?state.

Control of data flow from B to A is similar, but using the nEBA, nLEBA, and nOEBA inputs. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs

此產(chǎn)品已停產(chǎn)

Features and benefits

  • 16-bit universal bus interface

  • 3-state buffers

  • Wide supply voltage range from 2.7 V to 3.6 V

  • Input and output interface capability to systems at 5 V supply

  • Overvoltage tolerant inputs to 5.5 V

  • Direct interface with TTL levels

  • BiCMOS high speed and output drive

  • Output capability: +64 mA/-32 mA

  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

  • Live insertion/extraction permitted

  • Power-up 3-state

  • Power-up reset

  • No bus current loading when output is tied to 5 V bus

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

  • Complies with JEDEC standards

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C

參數(shù)類(lèi)型

型號(hào) Package name
74LVT16543ADL SSOP56

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74LVT16543ADL 74LVT16543ADL,112
(935182750112)		 Obsolete LVT16543A SOT371-1
SSOP56
(SOT371-1) 		SOT371-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暫無(wú)信息
74LVT16543ADL,118
(935182750118)		 Obsolete LVT16543A 暫無(wú)信息
74LVT16543ADL,512
(935182750512)		 Obsolete LVT16543A 暫無(wú)信息
74LVT16543ADL,518
(935182750518)		 Obsolete LVT16543A 暫無(wú)信息

環(huán)境信息

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74LVT16543ADL 74LVT16543ADL,112 74LVT16543ADL rhf
74LVT16543ADL 74LVT16543ADL,118 74LVT16543ADL rhf
74LVT16543ADL 74LVT16543ADL,512 74LVT16543ADL rohs rhf rhf
74LVT16543ADL 74LVT16543ADL,518 74LVT16543ADL rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (7)

文件名稱(chēng) 標(biāo)題 類(lèi)型 日期
74LVT16543A 3.3 V 16-bit registered transceiver; 3-state Data sheet 2024-07-08
lvt16543a lvt16543a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT371-1 plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
lvt16 lvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱(chēng) 標(biāo)題 類(lèi)型 日期
lvt16543a lvt16543a IBIS model IBIS model 2013-04-09
lvt16 lvt16 Spice model SPICE model 2013-05-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.