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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVT16501ADGG

3.3 V LVT 18-bit universal bus transceiver; 3-state

The 74LVT16501A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.

Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs.

For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A-bus data is latched if CPAB is held at a HIGH or LOW level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW).

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

此產品已停產

Features and benefits

  • 18-bit bidirectional bus interface
  • 3-state buffers
  • Output capability: +64 mA to -32 mA
  • TTL input and output switching levels
  • Input and output interface capability to systems at 5 V supply
  • Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
  • Live insertion and extraction permitted
  • Power-up reset
  • Power-up 3-state
  • No bus current loading when output is tied to 5 V bus
  • Positive-edge triggered clock inputs
  • Latch-up protection:
    • JESD78: exceeds 500 mA
  • ESD protection:
    • MIL STD 883, method 3015: exceeds 2000 V
    • Machine model: exceeds 200 V

Applications

參數類型

型號 Package name
74LVT16501ADGG TSSOP56

封裝

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVT16501ADGG 74LVT16501ADGG,112
(935203030112)		 Obsolete LVT16501A Standard Procedure Standard Procedure SOT364-1
TSSOP56
(SOT364-1) 		SOT364-1 SSOP-TSSOP-VSO-WAVE
暫無信息
74LVT16501ADGG,118
(935203030118)		 Obsolete LVT16501A Standard Procedure Standard Procedure SOT364-1_118
74LVT16501ADGGS
(935203030512)		 Obsolete LVT16501A Standard Procedure Standard Procedure 暫無信息
74LVT16501ADGGY
(935203030518)		 Obsolete LVT16501A Standard Procedure Standard Procedure 暫無信息

環(huán)境信息

下表中的所有產品型號均已停產 。

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVT16501ADGG 74LVT16501ADGG,112 74LVT16501ADGG rohs rhf rhf
74LVT16501ADGG 74LVT16501ADGG,118 74LVT16501ADGG rohs rhf rhf
74LVT16501ADGG 74LVT16501ADGGS 74LVT16501ADGG rohs rhf rhf
74LVT16501ADGG 74LVT16501ADGGY 74LVT16501ADGG rohs rhf rhf
品質及可靠性免責聲明

文檔 (7)

文件名稱 標題 類型 日期
74LVT16501A 3.3 V LVT 18-bit universal bus transceiver; 3-state Data sheet 2006-05-18
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
lvt16501a lvt16501a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
lvt16 lvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名稱 標題 類型 日期
lvt16501a lvt16501a IBIS model IBIS model 2013-04-09
lvt16 lvt16 Spice model SPICE model 2013-05-07
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.