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Dual supply configurable multiple function gate
The 74AXP1T57 is a dual supply configurable multiple function gate with Schmitt-trigger inputs. It features three inputs (A, B and C), an output (Y) and dual supply pins (VCCI and VCCO). The inputs are referenced to VCCI and the output is referenced to VCCO. All inputs can be connected directly to VCCI or GND. VCCI can be supplied at any voltage between 0.7 V and 2.75 V and VCCO can be supplied at any voltage between 1.2 V and 5.5 V. This feature allows voltage level translation. The 74AXP1T57 can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer.
This device ensures very low static and dynamic power consumption across the entire supply range and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range:
VCCI: 0.7 V to 2.75 V
VCCO: 1.2 V to 5.5 V
Low input capacitance; CI = 0.6 pF (typical)
Low output capacitance; CO = 1.8 pF (typical)
Low dynamic power consumption; CPD = 0.6 pF at VCCI = 1.2 V (typical)
Low dynamic power consumption; CPD = 7.1 pF at VCCO = 3.3 V (typical)
Low static power consumption; ICCI = 0.5 μA (85 °C maximum)
Low static power consumption; ICCO = 1.8 μA (85 °C maximum)
High noise immunity
Complies with JEDEC standard:
JESD8-12A.01 (1.1 V to 1.3 V; A, B, C inputs)
JESD8-11A.01 (1.4 V to 1.6 V)
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A.01 (2.3 V to 2.7 V)
JESD8-C (2.7 V to 3.6 V; Y output)
JESD12-6 (4.5 V to 5.5 V; Y output)
ESD protection:
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM JESD22-C101E exceeds 1 kV
Latch-up performance exceeds 100 mA per JESD78D Class II
Inputs accept voltages up to 2.75 V
Low noise overshoot and undershoot < 10% of VCCO
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
參數(shù)類型
| 型號(hào) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) |
|---|---|---|---|---|---|---|
| 74AXP1T57GT | CMOS | ± 12 | 4.8 | 1 | ultra low | -40~85 |
封裝
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AXP1T57GT | 74AXP1T57GTX (935305668115) |
Obsolete | no package information | ||||
環(huán)境信息
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AXP1T57GT | 74AXP1T57GTX | 74AXP1T57GT |
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文檔 (6)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AXP1T57 | Dual supply configurable multiple function gate | Data sheet | 2022-06-17 |
| AN90029 | Pin FMEA for AXPnT family | Application note | 2021-07-13 |
| Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
| axp1t57 | 74AXP1T57 IBIS model | IBIS model | 2016-03-01 |
| Nexperia_document_leaflet_Logic_AXP_technology_portfolio_201904 | AXP – Extremely low-power logic technology portfolio | Leaflet | 2019-04-05 |
| 74AXP1T57GT_Nexperia_Product_Reliability | 74AXP1T57GT Nexperia Product Reliability | Quality document | 2022-05-04 |
支持
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模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| axp1t57 | 74AXP1T57 IBIS model | IBIS model | 2016-03-01 |
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.