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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調(diào)節(jié)ESD保護

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認證產(chǎn)品(AEC-Q100/Q101)

74LV02PW

Quad 2-input NOR gate

The 74LV02 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC02 and 74HCT02.

The 74LV02 provides a quad 2-input NOR function.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide operating voltage: 1.0 V to 5.5 V

  • Optimized for low voltage applications: 1.0 V to 3.6 V

  • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

  • Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C

  • Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C

  • ESD protection:

    • HBM JESD22-A114E exceeds 2000 V

    • MM JESD22-A115-A exceeds 200 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Applications

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號，（訂購碼(12NC)） 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LV02PW 74LV02PW,112
(935174160112)		 Obsolete no package information

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74LV02PW 74LV02PW,112 74LV02PW rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (2)

文件名稱 標題 類型 日期
74LV02 Quad 2-input NOR gate Data sheet 2017-05-10
lv02 74LV02 IBIS model IBIS model 2019-01-09

支持

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模型

文件名稱 標題 類型 日期
lv02 74LV02 IBIS model IBIS model 2019-01-09

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.