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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74HCT112D-Q100

Dual JK flip-flop with set and reset; negative-edge trigger

The 74HC112-Q100; 74HCT112-Q100 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

Features and benefits

  • Input levels:

    • For 74HC112-Q100: CMOS level

    • For 74HCT112-Q100: TTL level

  • Asynchronous set and reset

  • Specified in compliance with JEDEC standard no. 7A

  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

參數(shù)類型

型號(hào) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Power dissipation considerations Tamb (°C) Package name
74HCT112D-Q100 4.5?-?5.5 TTL ± 4 19 70 low -40~125 SO16

封裝

型號(hào) 可訂購的器件編號(hào),(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74HCT112D-Q100 74HCT112D-Q100J
(935691595118)
Active 74HCT112D SOT109-1
SO16
(SOT109-1)
SOT109-1 SO-SOJ-REFLOW
SO-SOJ-WAVE
WAVE_BG-BD-1
SOT109-1_118

環(huán)境信息

型號(hào) 可訂購的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74HCT112D-Q100 74HCT112D-Q100J 74HCT112D-Q100 rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (10)

文件名稱 標(biāo)題 類型 日期
74HC_HCT112_Q100 Dual JK flip-flop with set and reset; negative-edge trigger Data sheet 2024-01-15
SOT109-1 3D model for products with SOT109-1 package Design support 2020-01-22
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SO16_SOT109-1_mk plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.35 mm body Marcom graphics 2017-01-28
SOT109-1 plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.75 mm body Package information 2023-11-07
SOT109-1_118 SO16; Reel pack for SMD, 13"; Q1/T1 product orientation Packing information 2024-02-19
74HCT112D-Q100_Nexperia_Product_Reliability 74HCT112D-Q100 Nexperia Product Reliability Quality document 2024-06-16
SO-SOJ-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SO-SOJ-WAVE Footprint for wave soldering Wave soldering 2009-10-08
WAVE_BG-BD-1 Wave soldering profile Wave soldering 2021-09-08

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
SOT109-1 3D model for products with SOT109-1 package Design support 2020-01-22

訂購、定價(jià)與供貨

型號(hào) Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74HCT112D-Q100 74HCT112D-Q100J 935691595118 Active SOT109-1_118 2,500 訂單產(chǎn)品

樣品

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如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號(hào) 可訂購的器件編號(hào) 訂購代碼(12NC) 封裝 從經(jīng)銷商處購買
74HCT112D-Q100 74HCT112D-Q100J 935691595118 SOT109-1 訂單產(chǎn)品
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