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Click here for more information74LVC2G32GD
Dual 2-input OR gate
The 74LVC2G32 is a dual 2-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
5 V tolerant outputs in the Power-down mode
±24 mA output drive (VCC = 3.0 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類(lèi)型
| 型號(hào) | Package name |
|---|---|
| 74LVC2G32GD | XSON8 |
封裝
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G32GD | 74LVC2G32GD,125 (935286857125) |
Withdrawn / End-of-life | V32 |
XSON8 (SOT996-2) |
SOT996-2 | SOT996-2_125 |
環(huán)境信息
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G32GD | 74LVC2G32GD,125 | 74LVC2G32GD |
|
|
Series
文檔 (6)
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| 74LVC2G32 | Dual 2-input OR gate | Data sheet | 2024-08-12 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| lvc2g32 | 74LVC2G32 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT996-2 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 3 mm x 2 mm x 0.5 mm body | Package information | 2020-04-21 |
支持
如果您需要設(shè)計(jì)/技術(shù)支持，請(qǐng)告知我們并填寫(xiě) 應(yīng)答表 我們會(huì)盡快回復(fù)您。
模型
| 文件名稱(chēng) | 標(biāo)題 | 類(lèi)型 | 日期 |
|---|---|---|---|
| lvc2g32 | 74LVC2G32 IBIS model | IBIS model | 2014-10-20 |
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC2G32GD
Dual 2-input OR gate
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| SKU | 庫(kù)存* | MOQ | 單位價(jià)格 | 數(shù)量 |
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